Clock pulse and data regenerator for different data rates

ABSTRACT

A clock and data regenerator for different data rates including a control loop which is controlled by a phase discriminator (PD) and two frequency discriminators. The first frequency discriminator enlarges the catchment range of the control loop. The second frequency discriminator determines the ratio of the bit rates of the clock signal and of the data signal. The second frequency discriminator sets the loop frequency divider appropriately, and supplies a control voltage for setting the oscillator until the first frequency discriminator can carry out this function.

BACKGROUND OF THE INVENTION

The present invention relates to a clock and data regenerator fordifferent data rates having a phase and frequency control device.

Phase locked loops are used in order to recover the clock signal from areceived binary signal, and to obtain a regenerated data signal usingthis clock signal.

In a clock regeneration device, the control loop is chosen to have anarrow bandwidth so that the frequency and phase remain constant even inthe event of a long sequence of zeros or ones. However, a stable phaselocked loop has a very narrow catchment range. Thus, the clock recoveryoperates only in a very narrow frequency range (i.e., essentially onlyone quite specific bit rate).

A phase locked loop (PLL) which has a phase discriminator and afrequency discriminator is described in “Frequency Detectors for PLLAcquisition in Timing and Carrier Recovery” by David G. Messerschmitt,IEEE Transaction Communication, Vol. COM-27, pp. 1288-1295, September1979. The frequency discriminator is first used to set the oscillatorfrequency approximately, and the phase angled between the clock signalthat is produced and the data signal is then kept constant via the phaselocked loop. In practice, these phase locked loops have a catchmentrange of approximately±30% of the data signal frequency (bit rate).

If the clock regeneration is intended to be used for different datarates, then the catchment range of the PLL is frequently inadequate.

An apparatus for obtaining a clock signal from a data signal using a bitrate identification device for the received data signal is described inLaid-Open Specification DE 197 04 299 A1. The bit rate identificationdevice is supplied with various reference signals, which allow the flankdensities of the received data signal and of the reference signals to becompared. The result of this comparison is used to set a frequencydivider in the feedback path such that the phase control becomessuccessfully effective. This apparatus is particularly suitable for asmall number of bit rates, which are known at the receiving end.

SUMMARY OF THE INVENTION

An object of the present invention is, therefore, to provide a clock anddata regenerator which reliably processes different bit rates of thedata signal without any gaps. The clock and data regenerator is intendedto be developed such that differently coded data signals can also beprocessed.

One advantage of the present invention is the universal applicability ofthe regenerator by virtue of its wide operating range. Generally, thereis no need for a reference clock, but such a clock can be used in orderto allow the frequency divider to be pre-set.

Another advantage is achieved by a further frequency discriminator,which sets a frequency divider arranged in the feedback loop of thecontrol loop and adjusts a comparison frequency, which is obtained fromthe oscillator frequency, to such an extent that it enters the catchmentrange of the first frequency discriminator.

In an embodiment, the frequency divider is adjusted in steps while, inalternative embodiments which operate at higher speeds, the divider canbe pre-set directly on the basis of the measurement results from thefurther frequency discriminator. The two frequency discriminators can,of course, be combined in the circuitry.

Additional features and advantages of the present invention aredescribed in, and will be apparent from, the following DetailedDescription of the Invention and the Figures.

BRIEF DESCRIPTION OF THE FIGURES.

FIG. 1 shows a clock and data regenerator according to an embodiment ofthe present invention. FIG. 2 shows an embodiment of a clock and dataregenerator according to the present invention. FIG. 3 shows anembodiment of a second frequency discriminator. FIG. 4 shows controlcharacteristics for discriminators.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows the outline circuit diagram of an embodiment of aregenerator according to the present invention, which has frequencycontrol and phase control.

The phase locked loop (PLL) is formed from a phase discriminator PD, aloop filter, a controllable oscillator 5 and a frequency divider 6,which produces a clock signal TS which is fed back to a second input ofthe phase discriminator PD. The data signal DSF is used as a referencesignal. This may be the data signal DS received at the signal input 1,or a data signal DSF derived from this signal in a signal conditioningdevice 9. This signal conditioning converts each flank of the datasignal to, for example, a positive flank. This may be expedient when thereceived data signal is an NRZ signal (non return to zero) and does nothave the desired fundamental frequency. The frequency control is carriedout by way of a first frequency discriminator FD1 and a second frequencydiscriminator FD2, to both of which the clock signal TS, which isemitted at the output of the frequency divider, is likewise supplied.The received data signal is also supplied to a decision maker 7, whichsamples it using the clock signal and emits it as a regenerated datasignal DSR at the data output 10. The clock signal is available at aclock signal output 8.

A controller 11 is also provided, which controls resynchronization andswitches the frequency divider 6 such that the nominal frequency of theclock signal can be reached by the pull-in range of the controllableoscillator.

The function of the clock and data regenerator will be explained on thebasis of an embodiment illustrated in FIG. 2. This embodiment has athird frequency discriminator FD3, to which an external reference signalKF is supplied. The frequency discriminator FD3 separately counts thenumber of flanks of the data signal DS and the number of flanks of thereference signal KF within a predetermined time period. It isadvantageous to set the oscillator frequency approximately to the centerof the pull-in range in advance. The controller uses the flank densitiesto determine the bit rate of the data signal and, initially, sets adivision ratio for the frequency divider 6 for which the secondfrequency discriminator FD2 can at least roughly set the nominalfrequency of the oscillator. The second frequency discriminator FD2supplies (since there are generally even greater frequency differencesbetween the reference signal and the clock signal after setting of thefrequency divider) a control signal RF2 to the loop filter 4, whichensures further adaptation. The second frequency discriminator FD2 hasan advantage of a very wide operating range. However, the secondfrequency discriminator FD2 may not be sufficiently accurate if thetransmission code is unknown, and the probability of a data flankoccurring is hence unknown. Since the second frequency discriminator FD2determines its control signal in the same way that the third frequencydiscriminator FD3 determines the bit rate of the data signal, the secondfrequency discriminator FD2 can also carry out its task.

The frequency discriminators FD2, FD3 ensure that the clock and dataregenerator can operate reliably for widely differing data signal bitrates.

The function of the second and third frequency discriminators FD2, FD3will now be explained in more detail. FIG. 3 shows an associated blockdiagram that illustrates a first counter 13, whose clock input issupplied with the data signal flanks (in each case one pulse for eachpositive and negative flank of an NRZ signal), and a second counter 14,which counts each positive flank of the clock signal TS (furthercounters may also be positioned upstream of these counters, so that onlyeach n-th flank is counted). At the end of one counting period, theresults are subtracted from one another in a subtractor 16, in order toobtain a control criterion which is dependent on the frequencydifference ΔB. The counters 13, 14 are then reset using a set pulse SET.A multiplier 15 (which is positioned downstream from one of thecounters) can act as a correction element in order to slightly correctthe count result of the signal flank counter. With stochastic NRZ data,the probability of the occurrence of a data flank is 0.5 per bit. Acontrol criterion RF2=2Z_(D)−Z_(TS) can be obtained by the secondfrequency discriminator by forming the differences between the countvalues of the data flanks and of the positive clock flanks.

The bit rate is B_(s)=2Z_(n)/T, where T is the measurement time, basedon the probability that the occurrence of a data flank is 0.5.

The measurement error is dependent on the number of measured bits, or onthe measurement time. Furthermore, the probability of the occurrence ofa data flank is exactly 0.5 only with stochastic NRZ-coded data. Fornormal transmission codes, the expected value for the occurrence of astep changeover is, however, between about 0.5 and about 0.625 per bitfor CMI code. Thus, it is possible for there to be a systematicmeasurement error SF, depending on the code. The top of FIG. 4 shows thecharacteristics for various codes. The solid characteristic shows thesystematic measurement error SF of the control signal. If a meanexpected value of about 0.5625 is assumed, then the error is somewhatmore than 10%. The second frequency discriminator thus indicates thatthe frequency control has a sufficient margin in order to achieve thecatchment range of about±30% of the data rate of the first frequencydiscriminator. A corresponding situation applies to the divider settingby way of the third frequency discriminator.

The controller 11 can use the count result to set the frequency dividerin the control loop on the basis of a stored table 18.

Other embodiments, including analog embodiments, are also, of course,feasible for the second and third frequency discriminators.

The pull-in range of the oscillator and the setting steps of thefrequency divider must be matched to one another. It must always bepossible to vary the oscillator frequency sufficiently that the secondfrequency discriminator FD2 is sufficient for rough frequency control,until the first frequency discriminator FD1 can then carry out the finefrequency adjustment. If the oscillator can be tuned, for example, overone octave, then it is possible to use a frequency divider which can beswitched in binary steps. The feasibility to switch off the outputsignals from the frequency discriminators depends on the embodiment andthe dimensioning.

Once the frequency has been set roughly by the frequency control signalRF2, the first frequency discriminator FD1 supplies a control signal RF1for a further approximation of the frequencies by the data signal andclock signal until the catchment range of the phase discriminator PD isreached. To this end, the first frequency discriminator FD1 compares thereference signal (data signal) and the comparison signal derived fromthe oscillator, the clock signal TS, and normally emits a frequencycontrol voltage RFI which is proportional to the frequency differenceΔB.

If the loop is locked in with locked phase angles, then it isadvantageous to switch off the frequency discriminators (via a switchingdevice 12 in FIGS. 1 and 2) since, otherwise, the phase jitter, whichcan likewise be perceived as a frequency change, via the loop filterwould result in additional control signals being supplied to theoscillator. Instead of switching off the control signals, a suitabledesign of the frequency discriminators can also be used to ensure thesame effect.

In order to achieve an optimum control response for the design of thePLL, it is advantageous for the loop filter to have a proportional pathP for the phase discriminator and at least one integral path I for thefrequency discriminators, whose output signals are combined by an adder17. In order to satisfy the stability conditions required for datatransmission, the filter parameters can be switched as a function of thedata rate.

The controller 11 can be equipped with a memory M1, M2, which keeps thesetting of the PLL constant if the data signal fails. Thus,resynchronization takes place very quickly.

A method of operation of the control process will be explained withreference to the control signals and FIG. 4. If the bit rate errors arelarge, the frequency control signal RF2=Z_(D−Z) _(TS) of the secondfrequency discriminator FD2 readjusts the frequency of the oscillator asa function of the difference ΔB in the bit rates between the data signaland the clock signal until the catchment range of the first frequencydiscriminator FD1 is reached. The amplitude becomes zero, and thefrequency control signal RF2 is switched off. The frequency controlsignal RF1 of the first frequency discriminator FD1 then ensuresaccurate matching of the frequencies, until the phase control is carriedout by the phase control signal RP of the phase discriminator PD.

The analyses described above are based on an objective measurement ofthe bit rate using a constant reference signal. However, this is notessential. In fact, in accordance with the embodiment illustrated inFIG. 1, it is also possible to use the one output clock of the frequencydivider 6 (i.e., the clock signal TS) as a reference signal. The secondfrequency discriminator FD2 then compares the clock signal with thedigital signal DSF, and once again passes on the control signal to thecontroller 11. The controller 11 knows the current divider setting andallows operation of the control loop at the bit rate of the applied datasignal. Thus, the controller can set the frequency divider directly.

The frequency divider setting can also be carried out successively, forexample, by checking the control signal determined by the secondfrequency discriminator. The setting of the frequency divider 6 isvaried in steps as a function of a positive or negative result goingbeyond a threshold value. The control signal of the oscillator 5 can, ofcourse, also be used as an equivalent measurement variable and can alsobe used to adjust the frequency divider 6 in the control cut-off regionsuch that the operating frequency of the oscillator is well away fromthe limit, for example, such that it is moved approximately to thecenter of the pull-in range. Such a limit situation can occur if thedivision ratio of the frequency divider has been set to a poor valueowing to the systematic error.

Although the present invention has been described with reference tospecific embodiments, those of skill in the art will recognize thatchanges may be made thereto without departing from the spirit and scopeof the invention as set forth in the hereafter appended claims.

What is claimed is:
 1. A clock and data regenerator for different datarates, comprising: a phase discriminator; a first frequencydiscriminator, a data signal being supplied as a reference signal toboth the phase discriminator and the first frequency discriminator anoscillator; a loop filter driving the oscillator; a frequency divider ina feedback path, an output signal from the frequency divider supplying acomparison signal to both the phase discriminator and the firstfrequency discriminator; and at least one second frequency discriminatorwhich compares a bit rate of the data signal to the output signal fromthe frequency divider, a comparison result of the second frequencydiscriminator supplying both a first control signal for controlling adivision ratio of the frequency divider and a second control signalwhich, after being filtered by the loop filter, controls the oscillator.2. A clock and data regenerator as claimed in claim 1, wherein thedivision ratio of the frequency divider is one of reduced and increasedbased on the comparison result of the second frequency discriminator. 3.A clock and data regenerator as claimed in claim 1, wherein the divisionratio of the frequency divider is set based on the comparison result ofthe second frequency discriminator.
 4. A clock and data regenerator asclaimed in claim 1, further comprising a controller, the controllerconverting the comparison result of the second frequency discriminatorto the first control signal that controls the division ratio of thefrequency divider, the controller also converting the comparison resultto the second control signal which, after being filtered by the loopfilter, controls the oscillator.
 5. A clock and data regenerator,comprising a phase discriminator; a first frequency discriminator, adata signal being supplied as a reference signal to both the phasediscriminator and the first frequency discriminator; an oscillator; aloop filter driving the oscillator; a frequency divider in a feedbackpath, an output signal from the frequency divider supplying a comparisonsignal to both the phase discriminator and the first frequencydiscriminator; a second frequency discriminator which compares a bitrate of the data signal to the output signal from the frequency divider,a comparison result of the second frequency discriminator beingconverted to a second control signal which, after being filtered by theloop filter, controls the oscillator; and a third frequencydiscriminator to which a constant reference signal is supplied todetermine the bit rate of the data signal, a comparison result of thethird frequency discriminator being converted to a first control signalfor controlling a division ratio of the frequency divider.
 6. A clockand data regenerator as claimed in claim 5, further comprising acontroller, the controller converting the comparison result of the thirdfrequency discriminator to the first control signal for controlling thedivision ratio of the frequency divider, the controller also convertingthe comparison result of the second frequency discriminator to thesecond control signal which, after being filtered by the loop filter,controls the oscillator.
 7. A clock and data regenerator as claimed inclaim 5, wherein the reference signal is periodically supplied to thesecond frequency discriminator to determine values for setting thefrequency divider.
 8. A clock and data regenerator as claimed in claim5, wherein the second frequency discriminator and the third frequencydiscriminator assess step changeovers of the data signal in comparisonto step changeovers of one of a clock signal, the reference signal ortime to determine one of the first control signal or the second controlsignal.
 9. A clock and data regenerator as claimed in claim 5, whereinat least one of the second frequency discriminator and the thirdfrequency discriminator includes a correction element for correcting ameasured data rate of the data signal.
 10. A clock and data regeneratoras claimed claim 5, wherein a control signal of at least one of thefrequency discriminators is one of switched off and not emitted in aregion of a nominal position.
 11. A clock and data regenerator asclaimed in claim 5, further comprising a setting device for setting theoscillator to a mid-frequency within a pull-in range of the oscillator,for resynchronization.
 12. A clock and data regenerator as claimed inclaim 5, wherein a loop filter is provided for each discriminator, theloop filter being in the form of one of an integrator and a filter withan integral component.
 13. A clock and data regenerator as claimed inclaim 5, further comprising a binary-adjustable frequency divider,wherein the oscillator includes a pull-in range of at least one octave.14. A clock and data regenerator as claimed in claim 5, furthercomprising a storage device for storing setting values of at least oneof the frequency divider and the oscillator, the setting values beingused as start values for resynchronization.
 15. A clock and dataregenerator as claimed in claim 5, wherein the loop filter has aproportionality path to which a control signal of the phasediscriminator is supplied, and the loop filter has at least one integralpath to which a control signal of at least one of the frequencydiscriminators is supplied.
 16. A clock and data regenerator as claimedclaim 5, wherein filter parameters for the loop filter are set as afunction of a data rate.
 17. A clock and data regenerator as claimed inclaim 5, further comprising a correcting device for correcting a settingof the frequency divider when a pull-in range of the oscillator reachesa limit value.
 18. A clock and data regenerator as claimed in claim 5,wherein signal conditioning converts a received data signal to the datasignal, the data signal being derived from received data signal at afundamental frequency of a data rate.